This line is specified by the caption position register (address 00E016). This line is specified by the data slicer control register 3 (address 00EB16). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matched the value specified by bits 4 to 0 of the caption position register (in case of the sub-data slice line, by bits 3 to 7 of the data slicer control register 3), this Hsep is sliced. The values of "0016" to "1F16" can be set in the caption position register. Bit 7 to bit 5 are used for testing. Set "1002." Figure 24 shows the signals in the vertical blanking interval. Figure 25 shows the structure of the caption position register. Table 3. Specifying of field whose sets reference voltage Bit 0 of DSC3 0 1 Field specified by bit 1 of DSC1 Field specified by bit 1 of DSC3 Field 0: F2 0: F2 1: F1 1: F1
Selection of field to be sliced data In the case of the main data slice line, the field to be sliced data is selected by bits 2 and 1 of the data slicer control register 1 (address 00EA16). In the case of the sub-data slice line, the field is selected by bits 2 and 1 of the data slicer control register 3. When bit 2 of the data slicer control register 1 is set to "1," it is possible to slice data of both fields (refer to Figure 20). Specification of line to set slice voltage The reference voltage for slicing (slice voltage) is generated by integrating the amplitude of the clock run-in pulse in the particular line (refer to Table 3). Field determination The field determination flag can be read out by bit 5 of the data slicer control register 1. This flag charge at the falling edge of Vsep.
Line Line specified by bits 4 to 0 of CP (Main data slice line) Line specified by bits 7 to 3 of DSC3 (Sub-data slice line)
DSC1 : Data slice control register 1 DSC3 : Data slice control register 3 CP : Caption position register
Video signal
Vertical blanking interval
Composite video signal Vsep
Line 21
Hsep Count value to be set in the caption position register ("1116" in this case)
Magnified drawing
Hsep Clock run-in Start bit + 16-bit data
Composite video signal
min. max. Time to be set in the start bit position register
Start bit
Fig. 24. Signals in vertical blanking interval
30
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(6) Reference Voltage Generating Circuit and Comparator
The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. Reference voltage generating circuit This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. Connect a capacitor between the VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be generated. Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value.
7 100
0 Caption position register (CP : address 00E016)
Specification main data slice line
Fix these bits to "1002"
Fig. 25. Structure of caption position register
(7) Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line specification circuit. For start bit detection, it is possible to select one of the following two types by using bit 1 of the clock run-in register 2 (address 00E716). After the lapse of the time corresponding to the set value of the start bit position register (address 00E116), the first rising of the composite video signal is detected as a start bit. The time is set in bits 0 to 6 of the start bit position register (address 00E116) (refer to Figure 26). Set a value fit for the following conditions. Figure 26 shows the structure of the start bit position register.
7
0 Start bit position register (SP : address 00E116) Start bit generating time Time from a falling of the horizontal synchronizing signal to occurrence of a start bit = 4 ! set value ("0016" to "7F16") ! reference clock period DSC1 bit 7 control bit 0 : Generation of 16 pulses 1 : Generation of 16 pulses and detection of clock run-in
Fig. 26. Structure of start bit position register
Time from the falling of the horizontal synchronizing signal to the last rising of the clock run-in
<
4 ! set value of the start bit position register ! reference clock period <
Time from the falling of the horizontal synchronizing signal to occurrence of the start bit
31
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
After a falling of the clock run-in pulse set in bits 2 to 0 of clock runin detect register 2 (address 00E916) is detected, a start bit is detected by sampling a comparator output. A sampling clock for sampling is obtained by dividing the reference clock generated in the timing signal generating circuit by 13. Figure 28 shows the structure of clock run-in detect register 2. The contents of bits 2 to 0 of clock run-in detect register 2 and bit 1 of clock run-in register 2 are written at a falling of the horizontal synchronizing signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal.
7
0 Clock run-in detect register 2 (CRD2 : address 00E916)
7 100111
0 1 Clock run-in register 2 (CR2 : address 00E716) Fix this bit to "1" Start bit detecting method selection bit 0 : Method 1 1 : Method 2 Fix these bits to "1001112"
Clock run-in pulses for sampling b2 b1 b0 0 0 0 : Not available 0 0 1 : 1st pulse 0 1 0 : 2nd pulse 0 1 1 : 3rd pulse 1 0 0 : 4th pulse 1 0 1 : 5th pulse 1 1 0 : 6th pulse 1 1 1 : 7th pulse Data clock generating time Time from detection of a start bit to occurrence of a data clock = (13 + set value) ! reference clock period Fig. 28. Structure of clock run-in detect register 2
Fig. 27. Structure of clock run-in register 2
(8) Clock run-in determination circuit
This circuit sets a window in the clock run-in portion in the composite video signal, and then determinates clock run-in by counting the number of pulses in this window. Set the time from a falling of the horizontal synchronizing signal to a start of the window by bits 0 to 5 of the window register (address 00E216; refer to Figure 29). The window ends according to the contents of the setting of the start bit position register (refer to Figure 26). 7 00 0 Window register (WN : address 00E216) Window start time Time from a falling of the horizontal synchronizing signal to a start of the window = 4 ! set value ("0016" to "3F16") ! reference clock period Fix these bits to "0" Fig. 29. Structure of window register
32
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
For the main data slice line, the count value of pulses in the window is stored in clock run-in register 1 (address 00E616; refer to Figure 30). For the sub-data slice line, the count value of pulses in the window is stored in clock run-in register 3 (address 020916; refer to Figure 29). When this count value is 4 to 6, it is determined as a clock run-in. Accordingly, set the count value so that the window may start after the first pulse of the clock run-in (refer to Figure 32). The contents to be set in the window register are written at a falling of the horizontal synchronizing signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal. For the main data slice line, reference clock is counted in the period from a falling of the clock pulse set in bits 0 to 2 of the clock run-in detect register 2 (address 00E916) to the next falling. The count value is stored in bits 3 to 7 of the clock run-in detect register 1 (address 00E816) (When the count value exceeds "1F16," "1F16" is held). For the sub-data slice line, the count value is stored in bits 3 to 7 of the clock run-in detect register 3 (address 020816). Read out these bits after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Generating Circuit). Figure 33 shows the structure of clock run-in detect registers 1 and 3.
7 0101
0 Clock run-in register 1 (CR1 : address 00E616) Clock run-in count value of main-data slice line Fix these bits to "01012"
Fig. 30. Structure of clock run-in register 1
7 0 Clock run-in register 3 (CR3 : address 020916) Clock run-in count value of sub-data slice line
Data latch completion flag for caption data in sub-data slice line
0: Data is not latched yet 1: Data is latched Data slice line selection bit for interrupt request
0: Main data slice line 1: Sub-data slice line
Interrupt mode selection bit
0: Interrupt occurs at end of data slice line 1: Interrupt occurs at completion of caption data latch
Fig. 31. Structure of clock run-in register 3 Horizontal synchronizing signal Composite video signal Window Time to be set in the window register Time to be set in the start bit position register Fig. 32. Window setting 7 0 Clock run-in detect registers 1, 3 ( CRD1 : address 00E816) ( CRD3 : address 020816) Test bits : read-only VWhen the count value in the window is 4 to 6, this is determined as a clock run-in.
Clock run-in
Start bit data + 16-bit data
Number of reference clocks to be counted in one clock run-in pulse period Fig. 33. Structure of clock run-in detect registers 1and 3
33
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(9) Data clock generating circuit
This circuit generates a data clock phase-synchronized with the start bit detected in the start bit detecting circuit. Set the time from detection of the start bit to occurrence of the data clock in bits 3 to 7 of the clock run-in detect register 2 (address 00E916). The time to be set is represented by the following expression: Time = (13 + set value) ! reference clock period
For a data clock, 16 pulses are generated. When just 16 pulses have been generated, bit 7 of the data slicer control register is set to "1" (refer to Figure 20). When method 1 is already selected as a start bit detecting method, this bit becomes a logical product (AND) value with a clock run-in determination result by setting bit 7 of the start bit position register to "1." When method 2 is already selected as a start bit detecting method and 16 pulses are generated of a data clock regardless of bit 7 of the start bit position register, this bit is set to "1." The contents of this bit are reset at a falling of the vertical synchronizing signal (Vsep).
Table 4. Setting conditions for caption data latch completion flag Bit 7 of SP 0 1 Conditions for setting bit 7 of DSC1 to "1" Data clock of 16 pulses has occured in main data slaice line Data clock of 16 pulses has occured in main data slaice line AND Clock run-in pulse are detected 4 to 6 times Conditions for setting bit 4 of DSC3 to "1" Data clock of 16 pulses has occured in sub-data slaice line Data clock of 16 pulses has occured in sub-data slaice line AND Clock run-in pulse are detected 4 to 6 times
(10) 16-bit Shift Register
The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. For the main data slice line, the contents of the high-order 8 bits of the stored caption data and the contents of the low-order 8 bits of the same data can be obtained by reading out the data register 2 (address 00E516) and data register 1 (address 00E416), respectively. For the sub-data slice line, the contents of the high-order 8 bits and the contents of the low-order 8 bits can be obtained by reading out the data register 4 (address 00ED16) and the data register 3 (address 00EC16), respectively. These registers are reset to "0" at a falling of Vsep. Read out data registers 1 and 2 after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Generating Circuit). Table 5. Occurence sources of interrupt request CR3 b5 b6 0 0 0 1 1 0 0 1 1 1 1 0 Sub-data slice line CR2 b1 0 1 Main data slice line
(11) Interrupt Request Generating Circuit
The occurence sources of interrupt request are selected by combination of the following bits; bits 5 and 6 of the clock run-in register 3 (address 020916), bit 1 of the clock run-in register 2 (address 00E716) (refer to Table 6). Read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect registers 1 and 3 after the occurence of a data slicer interrupt request.
Occurence souces of interrupt request Slice line At end of data slice line Data clock of 16 pulses has occured AND Clock run-in pulse are detected 4 to 6 times Data clock of 16 pulses has occured At end of data slice line Data clock of 16 pulses has occured AND Clock run-in pulse are detected 4 to 6 times Data clock of 16 pulses has occured Sources
34
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(12) Synchronizing Signal Counter
The synchronizing signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronizing signal Vsep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds "1F16," "1F16" is stored into the latch. The latch value can be obtained by reading out the sync pulse counter register (address 00EA16). A count source is selected by bit 5 of the sync pulse counter register. The synchronizing signal counter is used when bit 0 of the PWM mode register 1 (address 02EA16). Figure 34 shows the structure of the sync pulse counter and Figure 35 shows the synchronizing signal counter block diagram. 7 0 Sync pulse counter register (SYC : address 00EA16) Count value
Count source 0: HSYNC signal 1: Composite sync signal
Count time
f(XIN)/213 (1024 s, f(XIN) = 8 MHz)
Fig. 34. Sync pulse counter register
f(XIN)/213
Composite sync signal HSYNC signal
Reset 5-bit counter Counter
b5 Selection gate : connected to black colored side when reset.
Latch (5 bits)
Sync pulse counter register
Data bus
Fig. 35. Synchronizing signal counter block diagram
35
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I2C-BUS INTERFACE
The multi-master interface is a circuit for serial communications conformed with the Philips I2C-BUS data transfer format. This interface, having an arbitration lost detection function and a synchronous function, is useful for serial communications of the multi-master. Figure 36 shows a block diagram of the multi-master I2C-BUS interface and Table 6 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I 2C control register, the I2C status register and other control circuits. I2C-BUS
Table 6. Multi-master I2C-BUS interface functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz)
Format
Communication mode
SCL clock frequency
: System clock = f(XIN)/2 Note: We are not responsible for any third party's infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I 2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
b7 S0D
I2 C address register
b0
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
b7
I 2C data shift register S0
b0 b7
MST TRX BB PIN
b0
AL AAS AD0 LRB
AL circuit
S1
Internal data bus
I C status register
2
BB circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
b7 S2 I 2 C clock control register
Clock division
b0
b7
BSEL1 BSEL0 10BIT SAD ALS
b0
ES0 BC2 BC1 BC0
ACK ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
S1D I 2 C clock control register
System clock ( ) Bit counter
Fig. 36. Block diagram of multi-master I2C-BUS interface
36
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(1) I2C Data Shift Register
The I 2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ES0 bit of the I 2C control register (address 00F916) is "1." The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 00F816) are "1," the SCL is output by a write instruction to the I2 C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
7
0 I2 C address register (S0D: address 00F716) Read/write bit Slave address
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Fig. 37. Structure of I2C address register
(3) I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. s Bits 0 to 4: SCL frequency control bits (CCR0-CCR4) These bits control the SCL frequency. Refer to Table 7. s Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0," the standard clock mode is set. When the bit is set to "1," the high-speed clock mode is set. s Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clockV is generated. When this bit is set to "0," the ACK return mode is set and make SDA "L" at the occurrence of an ACK clock. When the bit is set to "1," the ACK non-return mode is set. The SDA is held in the "H" status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = "0," the SDA is automatically made "L" (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made "H"(ACK is not returned). VACK clock: Clock for acknowledgement s Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to "0," the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to "1," the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA "H") and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I 2C clock control register during transmitting. If data is written during transmitting, the I2C clock generator is reset, so that data cannot be transmitted normally.
The I2C address register (address 00F716) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. s Bit 0: Read/write bit (RBW) Not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2 C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected. s Bits 1 to 7: Slave address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
(2) I2C Address Register
37
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
7
ACK
0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
I2C clock control register (S2 : address 00FA16) SCL frequency control bits Refer to Table 7. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock
Fig. 38. Structure of I2C clock control register Table 7. Set values of I2C clock control register and SCL frequency Setting value of SCL frequency CCR4-CCR0 (at = 4MHz, unit : kHz) Standard clock High-speed clock CCR4 CCR3 CCR2 CCR1 CCR0 mode mode
0 0 0 0 0 0 0
...
0 0 0 0 0 0 0
...
0 0 0 0 1 1 1
...
0 0 1 1 0 0 1
...
0 1 0 1 0 1 0
...
Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled 100 83.3 500/CCR value 17.2 16.6 16.1
Setting disabled Setting disabled Setting disabled 333 250 400(Note) 166 1000/CCR value 34.5 33.3 32.3
1 1 1
1 1 1
1 1 1
0 1 1
1 0 1
The I2C control register (address 00F916) controls data communication format. s Bits 0 to 2: Bit counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits. s Bit 3: I 2C interface use enable bit (ES0) This bit enables to use the multimaster I2C BUS interface. When this bit is set to "0," the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to "1," use of the interface is enabled. When ES0 = "0," the following is performed. PIN = "1," BB = "0" and AL = "0" are set (they are bits of the I2C status register at address 00F816 ). Writing data to the I2C data shift register (address 00F616) is disabled. s Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "(5) I2C Status Register," bit 1) is received, transmission processing can be performed. When this bit is set to "1," the free data format is selected, so that slave addresses are not recognized. s Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2 C address register (address 00F716) are compared with address data. When this bit is set to "1," the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. s Bits 6 and 7: Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 39).
(4) I2C Control Register
* *
Note: At 400 kHz in the high-speed clock mode, the duty is 40%. In the other cases, the duty is 50%.
38
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
"0" "1" BSEL0 SCL1/P11 SCL Multi-master I2C-BUS interface SDA "0" "1" BSEL1 SCL2/P12 "0" "1" BSEL0 SDA1/P13 "0" "1" BSEL1 SDA2/P14
7
BSEL1 BSEL0 10 BIT ALS SAD
0
ES0 BC2 BC1 BC0
I2C control register (S1D : address 00F916) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0 :8 0 0 1 :7 0 1 0 :6 0 1 1 :5 1 0 0 :4 1 0 1 :3 1 1 0 :2 1 1 1 :1 I2C-BUS interface use enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format Connection control bits between I2C-BUS interface and ports b7 b6 Connection port 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1, SCL2, SDA2
Note: When using multi-master I2C-BUS interface, set bits 3 and 4 of the serial I/O mode register (address 021316) to "1." Fig. 39. Connection port control by BSEL0 and BSEL1
(5) I2C Status Register
I2C
The status register (address 00F816) controls the interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. s Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616). s Bit 1: General call detecting flag (AD0) This bit is set to "1" when a general callV whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition. VGeneral call: The master transmits the general call address "0016" to all slaves. s Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data. In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions. The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). A general call is received. In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition. When the address data is compared with the I 2C address register (8 bits consisted of slave address and RBW), the first bytes agree. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616).
I2C-BUS
Fig. 40. Structure of I2C control register
* * *
39
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s Bit 3: Arbitration lostV detecting flag (AL) In the master transmission mode, when the SDA is made "L" by any other device, arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0," so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." In the case arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. VArbitration lost: The status in which communication as a master is disabled. s Bit 4: I 2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from "1" to "0." At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to "0" in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is "0," the SCL is kept in the "0" state and clock generation is disabled. Figure 42 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in one of the following conditions. Executing a write instruction to the I2 C data shift register (address 00F616). When the ES0 bit is "0" At reset The conditions in which the PIN bit is set to "0" are shown below: Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) Immediately after completion of 1-byte data reception In the slave reception mode, with ALS = "0" and immediately after completion of slave address or general call address reception In the slave reception mode, with ALS = "1" and immediately after completion of address data reception s Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to "0," this bus system is not busy and a START condition can be generated. When this bit is set to "1," this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to "1" by detecting a START condition and set to "0" by detecting a STOP condition. When the ES0 bit of the I2C control register (address 00F916) is "0" and at reset, the BB flag is kept in the "0" state. s Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is "0," the reception mode is selected and the data of a transmitting device is received. When the bit is "1," the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2 C control register (address 00F916) is "0" in the slave reception mode is selected, the TRX bit is set to "1" (transmit) if the least significant bit (R/W bit) of the address data trans-
* * * * * * *
mitted by the master is "1." When the ALS bit is "0" and the R/W bit is "0," the TRX bit is cleared to "0" (receive). The TRX bit is cleared to "0" in one of the following conditions. When arbitration lost is detected. When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). With MST = "0" and when a START condition is detected. With MST = "0" and when ACK non-return is detected. At reset s Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is "0," the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1," the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to "0" in one of the following conditions. Immediately after completion of 1-byte data transmission when arbitration lost is detected When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). At reset
* * * * * *
* * * *
Note: The START condition duplication prevention function disables the occurence of a START condition, reset of bit counter and SCL output when the following condition is satisfied: * a START condition is set by another master device.
40
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(6) START Condition Generating Method
7 0 I2C status register MST TRX BB PIN AL AAS AD0 LRB (S1 : address 00F816) Last receive bit (Note) 0 : Last bit = "0" 1 : Last bit = "1" General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected I2C-BUS interface interrupt request bit 0 : Interrupt request issued 1 : No interrupt request issued Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode Note: These bit and flags can be read out but cannot be written.
When the ES0 bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) for setting the MST, TRX and BB bits to "1." Then a START condition occurs. After that, the bit counter becomes "0002" and an SCL for 1 byte is output. The START condition generating timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 43, the START condition generating timing diagram, and Table 8, the START condition/STOP condition generating timing table.
I2C status register write signal SCL SDA BB flag Setup time Fig. 43. START condition generating timing diagram Setup time Hold time Set time for BB flag
(7) STOP Condition Generating Method
When the ES0 bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) for setting the MST bit and the TRX bit to "1" and the BB bit to "0". Then a STOP condition occurs. The STOP condition generating timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 44, the STOP condition generating timing diagram, and Table 8, the START condition/STOP condition generating timing table.
Fig. 41. Structure of I2C status register
I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag
SCL PIN
Fig. 44. STOP condition generating timing diagram
IICIRQ
Fig. 42. Interrupt request signal generating timing
Table 8. START condition/STOP condition generating timing table Item Standard clock mode High-speed clock mode Setup time 5.0 s (20 cycles) 2.5 s (10 cycles) Hold time 5.0 s (20 cycles) 2.5 s (10 cycles) Set/reset time 3.0 s (12 cycles) 1.5 s (6 cycles) for BB flag Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
41
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(8) START/STOP Condition Detecting Conditions
The START/STOP condition detecting conditions are shown in Figure 45 and Table 9. Only when the 3 conditions of Table 9 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "IICIRQ" occurs to the CPU.
(9) Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "0." The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 46, (1) and (2). 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "1." An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address 00F716) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit.
SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time Hold time
Fig. 45. START condition/STOP condition detecting timing diagram Table 9. START condition/STOP condition detecting conditions High-speed clock mode Standard clock mode 1.0 s (4 cycles) < SCL 6.5 s (26 cycles) < SCL release time release time 3.25 s (13 cycles) < Setup time 0.5 s (2 cycles) < Setup time 3.25 s (13 cycles) < Hold time 0.5 s (2 cycles) < Hold time Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
S
Slave address R/W
A
Data
A
Data
A/A
P
7 bits "0" 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
A
P
7 bits "1" 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte
S
A
A
Data
A
Data
A/A
P
7 bits "0" 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits
S
A
A
Sr
Data
A
Data 1 to 8 bits
A
P
7 bits "0" 8 bits 7 bits "1" 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit
From master to slave From slave to master
Fig. 46. Address data communication format
42
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to "1." After the second-byte address data is stored into the I 2C data shift register (address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd byte matches the slave address, set the RBW bit of the I2C address register (address 00F716) to "1" by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2 C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 46, (3) and (4).
*When all transmitted addresses are "0" (general call) AD0 of the I2C status register (address 00F816) is set to "1" and an interrupt request signal occurs. *When the transmitted addresses match the address set in AAS of the I2C status register (address 00F816) is set to "1" and an interrupt request signal occurs. *In the cases other than the above AD0 and AAS of the I2 C status register (address 00F816) are set to "0" and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00F616). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends.
(10) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and "0" in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (address 00FA16). Set "1016" in the I 2C status register (address 00F816) and hold the SCL at the "H" level. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00F616) and set "0" in the least significant bit. Set "F016" in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step . Set "D016" in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition occurs.
(11) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and "0" in the RBW bit. Set the no ACK clock mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (address 00FA16). Set "1016" in the I 2C status register (address 00F816) and hold the SCL at the "H" level. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). When a START condition is received, an address comparison is made.
43
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD FUNCTIONS
Table 10 outlines the OSD functions of the M37270MF-XXXSP. The M37270MF-XXXSP incorporates an OSD control circuit of 40 characters ! 16 lines. OSD is controlled by the OSD control register. There are 3 display modes and they are selected by a block unit. The display modes are selected by the block control register i (i = 1 to 6). The features of each mode are described below.
Table 10. Features of each display mode Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Pre-divide ratio (Note) Dot size Attribute Character font coloring Raster coloring Character background coloring Border coloring Extra font coloring OSD output Function R, G, B, OUT1, OUT2 Auto solid space function Window function Dual layer OSD function (layer 1) Possible R, G, B, I1, OUT1, OUT2 Dual layer OSD function (layer 2) CC mode (Closed caption mode) 40 characters ! 16 lines Display mode OSD mode (On-screen display mode) 40 characters ! 16 lines EXOSD mode (Extra on-screen display mode) 40 characters ! 16 lines
16 ! 26 dots 16 ! 26 dots 16 ! 20 dots (Character : 20 ! 16 dots) 320 kinds (In EXOSD mode, they can be combined with 32 kinds of extra fonts) 6 kinds 2 kinds 14 kinds ! 1, ! 2, ! 3 ! 1, ! 2 ! 1, ! 2, ! 3 1TC ! 1/2H Smooth italic, under line, flash 1 screen : 7 kinds, Max. 7 kinds (a character unit) 1TC ! 1/2H, 1TC ! 1H, 1.5TC ! 1/2H, 1.5TC ! 1H, 2TC ! 2H, 3TC ! 3H Border 1 screen : 7 kinds, Max. 15 kinds (a character unit) 1TC ! 1/2H, 1TC ! 1H Border, extra font (32 kinds) 1 screen : 7 kinds, Max. 7 kinds (a character unit)
Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Possible (a character unit, 1 screen Possible (a character unit, 1 screen Possible (a character unit, 1 screen : : 7 kinds, max. 7 kinds) : 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) R, G, B, I1, I2, OUT1, OUT2
Display expansion Possible Possible (multiline display) Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as "pre-divide ratio" hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to (3) Dote size).
44
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 47 shows the configuration of OSD character. Figure 48 shows the block diagram of the OSD control circuit. Figure 49 shows the structure of the OSD control register. Figure 50 shows the structure of the block control register.
CC mode OSD mode
16 dots 16 dots Blank area
*
26 dots 20 dots
20 dots
A(c) Underline area A(c) Blank area
*
*
*
16 dots 16 dots
: Displayed only in CCD mode.
EXOSD mode
16 dots
20 dots
logical sum (OR)
Character font
26 dots
Extra font
Fig. 47. Configuration of OSD character
26 dots
45
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Clock for OSD OSC1 OSC2 HSYNC VSYNC
Data slicer clock
Display oscillation circuit
Control registers for OSD OSD Control circuit OSD control register Horizontal position register Block control registers Clock source control register I/O polarity control register Raster color register Extra font color register Border color register Window H/L registers Vertical registers (address 00CE16) (address 00CF16) (addresses 00D016 to 00DF16) (address 021616) (address 021716) (address 021816) (address 021916) (address 021B16) (addresses 021C16 to 021F16) (addresses 022016 to 023F16)
RAM for OSD 20-bit ! 40 ! 16
RAM for OSD (16-bit! 20! 320) + 16-bit ! 26 ! 32)
Shift register 1 16-bit Output circuit Shift register 2 16-bit
R
G
B
I1
I2
OUT1 OUT2
Data bus Fig. 48. Block diagram of OSD control circuit
46
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
7
7
0
0 Block control register i (i = 1 to 16) (BCi : addresses 00D016 to 00DF) Display mode selection bits
OSD control register (OC : address 00CE16) OSD control bit (Note 1) 0 : All-blocks display off 1 : All-blocks display on Scan mode selection bit 0 : Normal scan mode 1 : Bi-scan mode Border type selection bit 0 : All bordered 1 : Shadow bordered (Note 2) Flash mode selection bit 0 : Color signal of character background part does not flash 1 : Color signal of character background part flashes Automatic solid space control bit 0 : OFF 1 : ON Window control bit 0 : OFF 1 : ON Layer mixing control bits (Note 3)
b7 b6
b1 b0
0 0 1 1
0 : Display OFF 1 : OSD mode 0 : CC mode 1 : EXOSD mode
Border control bit 0 : Border OFF 1 : Border ON Dot size selection bit Refer to Table 11. Pre-divide ratio * layer selection bits Refer to Table 11. OUT 2 output control bit (Note) 0 : OUT2 output OFF 1 : OUT2 output ON Notes : Bit 4 of the color code 1 controls OUT1 output when bit 7 is "0." Bit 4 of the color code 1 controls OUT2 output when bit 7 is "1."
0 0 : Logical sum (OR) of layer 1's color and layer 2's color 0 1 : Layer 1's color has priority 1 0 : Layer 2's color has priority 1 1 : Do not set Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : Set "00" during displaying extra fonts.
Fig. 50. Structure of block control registers
Table 11. Setting value of block control registers Fig. 49. Structure of OSD control register b6 b5 b4 b3 CS6 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 1 1 -- -- 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 !2 0 !1 -- !3 -- !2 Pre-divide ratio Dot size 1TC ! 1/2H -- !1 1TC ! 1H 2TC ! 2H 3TC ! 3H 1TC ! 1/2H 1TC ! 1H 2TC ! 2H 3TC ! 3H 1TC ! 1/2H 1TC ! 1H 2TC ! 2H 3TC ! 3H 1TC ! 1/2H 1TC ! 1H 1TC ! 1/2H 1TC ! 1H 1.5TC ! 1/2H 1.5TC ! 1H Layer 2 Layer 1 Display layer
0
0
Notes 1: CS6 : Bit 6 of clock control register (Address 021616) 2: TC : OSD clock cycle divided in the pre-divide circuit 3: H : HSYNC
47
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(1) Dual Layer OSD
M37270MF-XXXSP has 2 layers; layer 1 and layer 2. These layers display the OSD for controlling TV and the closed caption display at the same time and overlayed on each other. Each block can be assigned to either layer by bits 6 and 5 of the block control register (refer to Figure 50). For example, only when both bits 5 and 6 are "1," the block is assigned to layer 2. Other bit combinations assign the block to layer 1. When a block of layer 1 is overlapped with that of layer 2, a screen is combined (refer to Figure 52) by bits 7 and 6 of the OSD control register (refer to Figure 49). Note: When using the dual layer OSD, note Table 12.
Layer 2 Block 13 Block 14 Block 15 Block 16 Block Block 1 Block 2
Block 11 Block 12 Block Layer 1
...
Fig. 51. Image of dual layer OSD
Table 12. Conditions of dual layer Block Parameter Display mode OSD Clock source Pre-divide ratio Dot size Horizontal display start position Block in layer 1 CC mode Data slicer clock or OSC1 ! 1 or ! 2 (all blocks) 1TC ! 1/2H Arbitrary Block in layer 2 OSD mode Same as layer 1 Same as layer 1 (Note) Pre-divide ratio = 1 1TC ! 1/2H 1TC ! 1H Pre-divide ratio = 2 1TC ! 1/2H, 1.5TC ! 1/2H 1TC ! 1H, 1.5TC ! 1H
Same position as layer 1
Note: For the pre-divide ratio of the layer 2, select the same as the layer 1's ratio by bit 6 of the clock control register.
Display example of layer 1 = "HELLO," layer 2 = "CH5"
CH5 HELLO
CH5 HELLO
CH5 HELLO
Logical sum (OR) of layer 1's color and layer 2's color Bit 7 = "0," bit 6 = "0"
Layer 1's color has priority Bit 7 = "0", bit 6 = "1"
Layer 2's color has priority Bit 7 = "1," bit 6 = "0"
Fig. 52. Display example of dual layer OSD
48
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(2) Display Position
The display positions of characters are specified in units called a "block." There are 16 blocks, blocks 1 to 16. Up to 40 characters can be displayed in each block (refer to (6) Memory for OSD). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 TOSC (TOSC = oscillating cycle for OSD). The display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 TH ( TH = HSYNC cycle).
Blocks are displayed in conformance with the following rules: When the display position is overlapped with another block (Figure 53, (b)), a lower block number (1 to 16) is displayed on the front. When another block display position appears while one block is displayed (Figure 53 (c)), the block with a larger set value as the vertical display start position is displayed. However, do not display block with the dot size of 2TC ! 2H or 3TC ! 3H during display period ( V ) of another block. V In the case of OSD mode block: 20 dots in vertical from the vertical display start position. V In the case of CC or EXOSD mode block: 26 dots in vertical from the vertical display start position.
(HR) VP11, VP21 Block 1 VP12, VP22 Block 2 VP13, VP23 Block 3
(a) Example when each block is separated
(HR) VP11, VP21 VP12, VP22
Block 1 (Block 2 is not displayed)
(b) Example when block 2 overlaps with block 1
(HR) VP11, VP21 VP12, VP22 Block 1 Block 2 (c) Example when block 2 overlaps in process of block 1
Note: VP1i or VP2i (i : 1 to 16) indicates the contents of vertical position registers 1i or 2i.
Fig. 53. Display position
49
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, it starts to count the rising edge (falling edge) of HSYNC signal from after about 1 machine cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the I/O polarity control register (address 021716). For details, refer to (15) OSD Output Pin Control. Note: When bits 0 and 1 of the I/O polarity control register (address 021716) are set to "1" (negative polarity), the vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer (refer to Figure 54).
7
0
Vertical position register 1i (i = 1 to 16) (VP1i : addresses 022016 to 022F16) Control bits of vertical display start positions (Note) Vertical display start positions (low-order 8 bits) TH !(setting value of low-order 2 bits of VP2i !16 2 + setting value of low-order 4 bits of VP1i !16 1 + setting value of low-order 4 bits of VP1i !160 )
7
0
Vertical position register 2i (i = 1 to 16) (VP2i : addresses 023016 to 023F16) Control bits of vertical display start positions (Note) Vertical display start positions (high-order 2 bits) TH !(setting value of low-order 2 bits of VP2i !16 2 + setting value of low-order 4 bits of VP1i !16 1 + setting value of low-order 4 bits of VP1i !16 0)
VSYNC signal input
0.25 to 0.50 [s] ( at f(XIN) = 8MHz)
Note : Set values except "0016" and "0116" to VP1i when VP2i is "0016."
VSYNC control signal in microcomputer Period of counting HSYNC signal (Note 1) HSYNC signal input 1 2 3 4 5
Fig. 55. Structure of vertical position registers
Not count When bits 0 and 1 of the I/O polarity control register (address 021716) are set to "1" (negative polarity) Notes 1 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 2 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more.
The horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4TOSC, TOSC being the oscillating cycle for display) as values "0016" to "FF16" in bits 0 to 7 of the horizontal position register (address 00CF16). The structure of the horizontal position register is shown in Figure 56.
7
0
Fig. 54. Supplement explanation for display position
Horizontal position register (HP : address 00CF16)
Control bits of horizontal display start positions
The vertical position for each block can be set in 1024 steps (where each step is 1TH (TH: HSYNC cycle)) as values "0016" to "FF16" in vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16) and values "0016" to "FF16" in the vertical position register 2i (i = 1 to 16) (addresses 023016 to 023F16). The structure of the vertical position registers is shown in Figure 55.
Horizontal display start positions 4TOSC !(setting value of high-order 4 bits !16 1 + setting value of low-order 4 bits !160 ) Note : The setting value synchronizes with a rising (falling) of the VSYNC.
Fig. 56. Structure of horizontal position register
50
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different predivide ratios, their horizontal display start position will not match.
2 : The horizontal start position is based on the OSD clock source cycle selected for each block. Accordingly, when 2 blocks have different OSD clock source cycles, their horizontal display start position will not match.
HSYNC 1TC
Block 1 (Pre-divide ratio = 1, clock source = data slicer clock)
Note 1
4TOSC!N
1TC
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
1TC
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
Note 2
4TOSC'!N
1TC
Block 4 (Pre-divide ratio = 3, clock source = OSC1)
Fig. 57. Notes on horizontal display start position
(3) Dot Size
The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size of the layer 1 is specified by bits 6 to 3 of the block control register. The dot size of the layer 2 is specified by the following bits : bits 3 and 4 of the block control register, bit 6 of the clock source control register. Refer to Figure 50 (the structure of the block control regis-
ter), refer to Figure 59 (the structure of the clock source control register). The block diagram of dot size control circuit is shown in Figure 58. Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode. 2 : The pre-divide ratio of the OSD mode block on the layer 2 must be same as that of the CC mode block on the layer 1 by bit 6 of the clock source control register. 3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. Refer to "(13) Scan Mode" about the scan mode.
OSC1
Synchronization
circuit
Clock cycle = 1TC
Cycle!2 Cycle!3
Data slicer clock
CS0
Horizontal dot size control circuit
Pre-divide circuit HSYNC Vertical dot size control circuit OSD control circuit
Fig. 58. Block diagram of dot size control circuit
51
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(4) Clock for OSD
As a clock for display to be used for OSD, it is possible to select one of the following 3 types. Data slicer clock output from the data slicer (approximately 26 MHz) Clock from the LC oscillator supplied from the pins OSC1 and OSC2 Clock from the ceramic resonator or the quartz-crystal oscillator from the pins OSC1 and OSC2 This OSD clock for each block can be selected by the following bits : bit 7 of the port P3 direction register, bits 5 and 4 of the clock source control register (addresses 021616). A variety of character sizes can be obtained by combining dot sizes with OSD clocks. When not using the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins can be used as sub-clock I/O pins or port P6.
* * *
7
0
Clock source control register (CS : address 021616)
CC mode clock selection bit 0 : Data slicer clock 1 : OSC1 clock OSD mode clock selection bits
b2 b1
0 0 1 1
0 : Data slicer clock 1 : OSC1 clock 0: Do not set 1:
Table 13. Setting for P63/OSC1/XCIN, P64/OSC2/XCOUT Input Sub-clock OSD clock Function port I/O pin I/O pin Register b7 Port P3 direction register Clock source control register b5 b4 0 1 1 0 1 1 0 0 0 1 0 0 1
EXOSD mode clock selection bit 0 : Data slicer clock 1 : OSC1 clock OSD1 oscillating mode selection bits
b5 b4
0 0 1 1
0 : 32 kHZ oscillating mode 1 : Input ports P63, P64 0 : LC oscillating mode 1 : Ceramic * quartz-crystal oscillating mode
Pre-divide ratio of layer 2 selection bit 0:!1 1:!2 Test bit (Note) Note : Be sure to set bit 7 to "0" for program of the mask and the EPROM versions. For the emulator MCU version (M37270ERSS), be sure to set bit 7 to "1" when using the data slicer clock for software debugging.
Fig. 59. Structure of clock control register
Data slicer circuit 32 kHZ
"00"
Data slicer clock
"0"
CC mode block
"1" "0"
CS0
OSD mode block OSC1 clock LC
Ceramic * quartz-crystal "10" "1" "0"
CS1 CS2 = "0"
CS5, CS4
"11"
EXOSD mode block
"1"
CS3
Oscillating mode for OSD
Fig. 60. Block diagram of OSD selection circuit
52
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(5) Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 62) corresponding to the field is displayed alternately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC control signal (refer to Figure 54) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is regarded as odd field The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control register at address 021716). A dot line is specified by bit 6 of the I/O polarity control register (refer to Figure 62). However, the field determination flag read out from the CPU is fixed to "0" at even field or "1" at odd field, regardless of bit 6.
7 0 I/O polarity control register (PC : address 021716) HSYNC input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input VSYNC input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input R/G/B output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output I1, I2 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output OUT1 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output OUT2 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output Display dot line selection bit (Note) 0: " " at even field " " at odd field 1: " " at even field " " at odd field Field determination flag 0 : Even field 1 : Odd field
Note : Refer to Figure 62.
Fig. 61. Structure of I/O polarity control register
53
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Both HSYNC signal and VSYNC signal are negative-polarity input Field Display dot line determination selection bit flag(Note)
HSYNC
Field
Display dot line
VSYNC and VSYNC control signal in microcomputer Upper : VSYNC signal Lower : VSYNC control signal in microcomputer
(n - 1) field (Odd-numbered) T1
0.25 to 0.50[ms] at f(XIN) = 8 MHz
Odd
0 (n) field (Even-numbered) T2 Even 0 (T2 > T1) 1
Dot line 1 Dot line 0
0 (n + 1) field (Odd-numbered) T3 Odd 1 (T3 < T2) 1
Dot line 0
Dot line 1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A16) to "0." 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CC mode * EXOSD mode 2345 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OSD mode When the display dot line selection bit is "0," the " " font is displayed at even field, the " " font is displayed at odd field. Bit 7 of the I/O polarity control register can be read as the field determination flag : "1" is read at odd field, "0" is read at even field. 12 34 5 6 7 8 9 10 11 12 13 14 15 16
Character ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the VSYNC control signal (negative-polarity input) in the microcomputer.
Fig. 62. Relation between field determination flag and display font
54
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(6) Memory for OSD
There are 2 types of memory for OSD : ROM for OSD (addresses 1080016 to 1567F16, 1800016 to 1E43F16) used to store character dot data (masked) and RAM for OSD (addresses 080016 to 0FFF16) used to specify the characters and colors to be displayed. The following describes each type of memory. ROM for OSD (addresses 1080016 to 1567F16, 1800016 to 1E43F16) The ROM for OSD contains dot pattern data for characters to be displayed. To actually display the character code and the extra code stored in this ROM, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the ROM for OSD) into the RAM for OSD.
The OSD ROM of the character font has a capacity of 12800 bytes. Since 40 bytes are required for 1 character data, the ROM can stores up to 320 kinds of characters. The OSD ROM of the extra font has a capacity of 1664 bytes. Since 52 bytes are required for 1 character data, the ROM can stores up to 32 kinds of characters. Data of the character font and extra font is specified shown in Figure 63.
OSD ROM address of character font data
OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Font bit
Line number/character code/font bit
1
0
Line number
Character code
= "0216" to "1516" Line number Character code = "0016" to "13F16" Font bit = 0 : left font 1 : right font
OSD ROM address of extra font data
OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Font bit
Line number/extra code /font bit Line number Extra code Font bit Line number
0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516
1
1
Line number
0
0
0
0
Extra code
= "0016" to "1916" = "0016" to "1F16" = 0 : left font 1 : right font
b7
Left font
b0 b7
Right font
b0
Data in Line OSD number ROM
000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0016 0016 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916
b7
Left font
b0 b7
Right font
b0
Data in OSD ROM
FFFE16 FFFF16 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 FFFF16 FFFE16 000016 000016
Character font
Extra font
Fig. 63. OSD character data storing form
55
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
RAM for OSD (addresses 080016 to 0FFF16) The RAM for OSD is allocated at addresses 080016 to 0FFF16, and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. Table 14 shows the contents of the RAM for OSD. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write the color code 1 at 084016, and write the color code 2 at 082816. The structure of the RAM for OSD is shown in Figure 65.
Note: For the OSD mode block with dot size of 1.5TC ! 1/2H and 1.5TC ! 1H, the 3nth (n = 1 to 13) character is skipped as compared with ordinary blockV. Accordingly, maximum 26 characters are only displayed in 1 block. The RAM data for the 3nth character does not effect the display. Any character data can be stored here. V Blocks with dot size of 1TC ! 1/2H and 1TC ! 1H, or blocks on the layer 1
Table 14. Contents of OSD RAM Block Display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character code specification 080016 080116 : 081716 081816 : 082616 082716 088016 088116 : 089716 0E9816 : 08A616 08A716 090016 090116 : 091716 091816 : 092616 092716 098016 098116 : 099716 099816 : 09A616 09A716 0A0016 0A0116 : 0A1716 0A1816 : 0A2616 0A2716 Color code 1 specification 084016 084116 : 085716 085816 : 086616 086716 08C016 08C116 : 08D716 08D816 : 08E616 08E716 094016 094116 : 095716 095816 : 096616 096716 09C016 09C116 : 09D716 08D816 : 09E616 09E716 0A4016 0A4116 : 0A5716 0A5816 : 0A6616 0A6716 Color code 2 specification 082816 082916 : 083F16 086816 : 087616 087716 08A816 08A916 : 08BF16 08E816 : 08F616 08F716 092816 092916 : 093F16 096816 : 097616 097716 09A816 09A916 : 09BF16 09E816 : 09F616 09F716 0A2816 0A2916 : 0A3F16 0A6816 : 0A7616 0A7716
Block 1
Block 2
Block 3
Block 4
Block 5
56
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 14. Contents of OSD RAM (continued) Block Display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character code specification 0A8016 0A8116 : 0A9716 0A9816 : 0AA616 0AA716 0B0016 0B0116 : 0B1716 0B1816 : 0B2616 0B2716 0B8016 0B8116 : 0B9716 0B9816 : 0BA616 0BA716 0C0016 0C0116 : 0C1716 0C1816 : 0C2616 0C2716 0C8016 0C8116 : 0C9716 0C9816 : 0CA616 0CA716 0D0016 0D0116 : 0D1716 0D1816 : 0D2616 0D2716 Color code 1 specification 0AC016 0AC116 : 0AD716 0AD816 : 0AE616 0AE716 0B4016 0B4116 : 0B5716 0B5816 : 0B6616 0B6716 0BC016 0BC116 : 0BD716 0BD816 : 0BE616 0BE716 0C4016 0C4116 : 0C5716 0C5816 : 0C6616 0C6716 0CC016 0CC116 : 0CD716 0CD816 : 0CE616 0CE716 0D4016 0D4116 : 0D5716 0D5816 : 0D6616 0D6716 Color code 2 specification 0AA816 0AA916 : 0ABF16 0AE816 : 0AF616 0AF716 0B2816 0B2916 : 0B3F16 0B6816 : 0B7616 0B7716 0BA816 0BA916 : 0BBF16 0BE816 : 0BF616 0BF716 0C2816 0C2916 : 0C3F16 0C6816 : 0C7616 0C7716 0CA816 0CA916 : 0CBF16 0CE816 : 0CF616 0CF716 0D2816 0D2916 : 0D3F16 0D6816 : 0D7616 0D7716
Block 6
Block 7
Block 8
Block 9
Block 10
Block 11
57
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 14. Contents of OSD RAM (continued) Block Display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character code specification 0D8016 0D8116 : 0D9716 0D9816 : 0DA616 0DA716 0E0016 0E0116 : 0E1716 0E1816 : 0E2616 0E2716 0E8016 0E8116 : 0E9816 0E9916 : 0EA616 0EA716 0F0016 0F0116 : 0F1716 0F1816 : 0F2616 0F2716 0F8016 0F8116 : 0F9716 0F9816 : 0FA616 0FA716 Color code 1 specification 0DC016 0DC116 : 0DD716 0DD816 : 0DE616 0DE716 0E4016 0E4116 : 0E5716 0E5816 : 0E6616 0E6716 0EC016 0EC116 : 0ED716 0ED816 : 0EE616 0EE716 0F4016 0F4116 : 0F5716 0F5816 : 0F6616 0F6716 0FC016 0FC116 : 0FD716 0FD816 : 0FE616 0FE716 Color code 2 specification 0DA816 0DA916 : 0DBF16 0DE816 : 0DF616 0DF716 0E2816 0E2916 : 0E3F16 0E6816 : 0E7616 0E7716 0EA816 0EA916 : 0EBF16 0EE816 : 0EF616 0EF716 0F2816 0F2916 : 0F3F16 0F6816 : 0F7616 0F7716 0FA816 0FA916 : 0FBF16 0FE816 : 0FF616 0FF716
Block 12
Block 13
Block 14
Block 15
Block 16
Display sequence RAM address order
1 1
2 2
3 4
4 5
5 7
6 8
7
8
9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26
1.5Tc size block
10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32 34 35 37 38
Display sequence 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 1617 18 19 20 21 22 23 242526 27 28 29 30 31 32 3334 35 36 37 38 39 40 RAM address order 1Tc size
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2526 27 28 29 30 31 32 33 34 35 36 37 38 39 40 block
Fig. 64. RAM data for 3nth character
58
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Note: Do not read from and write to addresses in OSD RAM shown in Table 15.
Table 15. List of access disable addresses 087816 08F816 097816 09F816 0A7816 0AF816 0B7816 0BF816 0C7816 0CF816 0D7816 0DF816 0E7816 0EF816 0F7816 0FF816 087916 08F916 097916 09F916 0A7916 0AF916 0B7916 0BF916 0C7916 0CF916 0D7916 0DF916 0E7916 0EF916 0F7916 0FF916 087A16 08FA16 097A16 09FA16 0A7A16 0AFA16 0B7A16 0BFA16 0C7A16 0CFA16 0D7A16 0DFA16 0E7A16 0EFA16 0F7A16 0FFA16
59
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Blocks 1 to16 b7 RF7 RF6 RF5 RF4 RF3 RF2 b0 b7 b0 b3 b0
RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10 RC23 RC22 RC21 RC20
Character code
Color code 1
Color code 2
CC mode Bit RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC20 RC21 RC22 RC23 Not used Character code (High-order 1 bit) Control of character color R Control of character color G Control of character color B OUT1 control Flash control Underline control Italic control Control of background color R Control of background color G Control of background color B 0: Character output 1: Background output 0: Flash OFF 1: Flash ON 0: Underline OFF 1: Underline ON 0: Italic OFF 1: Italic ON Not used
0: Color signal output OFF 1: Color signal output ON
OSD mode Function Bit name Function
EXOSD mode Bit name Function
Bit name
Character code (Low-order 8 bits)
Specification of character code in OSD ROM
Character code (Low-order 8 bits)
Specification of character code in OSD ROM
Character code (Low-order 8 bits)
Specification of character code in OSD ROM
Character code (High-order 1 bit) Control of character color R Control of character color G Control of character color B OUT1 control Control of character color I1 0: Character output 1: Background output
0: Color signal output OFF 1: Color signal output ON 0: Color signal output OFF 1: Color signal output ON
Character code (High-order 1 bit) Character color code 0 (CC0) Character color code 1 (CC1) Character color code 2 (CC2) OUT1 control Extra code 0 Extra code 1 Extra code 2 (EX2)
0: Color signal output OFF Background color code 0 1: Color signal output ON
Specification of character color
0: Character output 1: Background output Specification of
(EX0) extra code in OSD ROM (EX1)
0: Color signal output OFF Control of background 1: Color signal output ON
Specification of
color R Control of background color G Control of background color B Control of background color I1
(BCC0) background color Background color code 1 (BCC1) Background color code 2 (BCC2) Extra code 3 Specification of (EX3) extra code in OSD ROM
Notes 1: Read value of bits 4 to 7 of the color code 2 is undefined. 2: For "not used" bits, the write value is read. 3: The decode value of the extra code is "EX4."
Fig. 65. Structure of OSD RAM
60
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(7) Character color
The color for each character is displayed by the color code 1. The kinds and specification method of character color are different depending on each mode. CC mode .................. 7 kinds Specified by bits 1 (R), 2 (G), and 3 (B) of the color code 1 OSD mode ............... 15 kinds Specified by bits 1 (R), 2 (G), 3 (B), and 5 (I1) of the color code 1 EXOSD mode .......... 7 kinds Specified by bits 1 (CC0), 2 (CC1), and 3 (CC2) of the color code 1 The correspondence Table of the color code 1 and color signal output in the EXOSD mode is shown in Table 16.
Table 16. Correspondence table of color code 1 and color signal output in EXOSD mode Color code 1 Bit 3 CC2 0 0 0 0 1 1 1 1 Bit 2 CC1 0 0 1 1 0 0 1 1 Bit 1 CC0 0 1 0 1 0 1 0 1 R 0 1 0 1 1 1 0 1 Color signal output G 0 0 1 1 1 1 1 1 B 0 0 0 0 0 1 1 1 I1 0 0 0 1 0 1 0 0 I2 0 0 0 0 1 0 0 0
* * *
(8) Character background color
The character background color can be displayed in the character display area. The character background color for each character is specified by the color code 2. The kinds and specification method of character background color are different depending on each mode. CC mode .................. 7 kinds Specified by bits 0 (R), 1 (G), and 2 (B) of the color code 2 OSD mode ............... 15 kinds Specified by bits 0 (R), 1 (G), 2 (B), and 3 (I1) of the color code 2 EXOSD mode .......... 7 kinds Specified by bits 0 (BCC0), 1 (BCC1), and 2 (BCC2) of the color code 2 The correspondence table of the color code 2 and color signal output in the EXOSD mode is shown in Table 17.
* * *
Table 17. Correspondence table of color code 2 and color signal output in EXOSD mode Color code 2 Bit 2 BCC2 0 0 0 0 1 1 1 1 Bit 1 BCC1 0 0 1 1 0 0 1 1 Bit 0 BCC0 0 1 0 1 0 1 0 1 R 0 1 0 1 1 1 0 1 Color signal output G 0 0 1 1 1 1 1 1 B 0 0 0 0 0 1 1 1 I1 0 0 0 1 0 1 0 0 I2 0 0 0 0 1 0 0 0
Note : The character background color is displayed in the following part : (character display area)-(character font)-(border)-(extra font). Accordingly, the character background color does not mix with these color signal.
61
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(9) OUT1, OUT2 signals
The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by bit 4 of the color code 1 (refer to Figure 65), bits 2 and
7 of the block control register (refer to Figure 50). The setting values for controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 66.
Block control register OUT2 output control bit (b7) Border output control bit (b2)
OUT1 control (b4 of color code 1)
Output waveform
0 0 1 0 0 1 1
OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2
0 0 1 1 0 1
OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1
1
OUT2
Fig. 66. Setting value for controlling OUT1, OUT2 and corresponding output waveform
62
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(10) Attribute
The attributes (flash, underline, italic) are controlled to the character font. The attributes for each character are specified by the color codes 1 and 2 (refer to Figure 65). The attributes to be controlled are different depending on each mode. CC mode ..................... Flash, underline, italic OSD mode .................. Border (all bordered, shadow bordered can be selected) EXOSD mode ............. Border (all bordered, shadow bordered can be selected) , extra font (32 kinds) Under line The underline is output at the 23th and 24th dots in vertical direction only in the CC mode. The underline is controlled by bit 6 of the color code 1. The color of underline is the same color as that of the character font. Flash The parts of the character font, the underline, and the character background are flashed only in the CC mode. The color signals (R, G, B, OUT1) of the character font and the underline are controlled by bit 5 of the color code 1. All of the color signals for the character font flash. However, the color signal for the character background can be controlled by bit 3 of the OSD control register (refer to Figure 49). The flash cycle bases on the VSYNC count. * VSYNC cycle ! 48 ] 800 ms (at flash ON) * VSYNC cycle ! 16 ] 267 ms (at flash OFF) Italic The italic is made by slanting the font stored in OSD ROM only in the CC mode. The italic is controlled by bit 7 of the color code 1. The display example of the italic and underline is shown in Figure 67. In this case, 16 26 dots are used and "R" is displayed. Notes 1: When setting both the italic and the flash, the italic character flashes. 2: When the pre-divide ratio = 1, the italic character with slant of 1 dot ! 5 steps is displayed (refer to Figure 68 (c)). When the pre-divide ratio = 2, the italic character with slant of 1/2 dot ! 10 steps is displayed (refer to Figure 68 (d)). 3: The boundary of character color is displayed in italic. However, the boundary of character background color is not affected by the italic (refer to Figure 69). 4: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 69). 5: When displaying the italic character in the block with the pre-divide ratio = 1, set the OSD clock frequency to 11 MHz to 14 MHz.
Extra font There are 32 kinds of the extra fonts configured with 16 ! 26 dots in OSD ROM. 16 kinds of these fonts can be displayed by ORed with the character font by a character unit (refer to Figure 47). For the others, only the extra font is displayed (refer to Figure 47). In only the EXOSD mode, the extra font is controlled the following : bits 7 to 5 of the color code 1, bit 3 of the color code 2, and decode value (EX4) of the character code. When the character code = "0016" to "13F16," EX4 is "0, " when the character code = "14016," EX4 is "1." Since there is no font with the character code = "14016," a blank is displayed. The extra font color for each screen is specified by the extra color register. When the character font overlaps with the extra font, the color of the area becomes the ORed color of both fonts. Note : When using the extra font, set bits 7 and 6 of the OSD control register to "0" (refer to Figure 49).
7
0 Extra font color register (RC : address 021916) Extra font color R control bit 0 : No output 1 : Output Extra font color G control bit 0 : No output 1 : Output Extra font color B control bit 0 : No output 1 : Output Extra font color I1 control bit 0 : No output 1 : Output Extra font color I2 control bit 0 : No output 1 : Output
Fig. 67. Structure of extra font color register
63
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Color code 1
Color code 1
Bit 6
Bit 7
Bit 6
Bit 7
0
0
1
0
(a) Ordinary
(b) Underline
Color code 1 Bit 6 Bit 7
Color code 1 Bit 6
Bit 7
0
1
0
1
(c) Italic (pre-divide ratio = 1)
(c) Italic (pre-divide ratio = 2)
Fig. 68. Example of attribute display (in CC mode)
Italic on one side
Italic on both sides
Bit 7 of color code 1
1
0
0
1
1
0
1
Note : The wavy-lined is the boundary of character color
Fig. 69. Example of italic display
64
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Border The border is output in the OSD mode and the EXOSD mode. The all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure 70) by bit 2 of the OSD control register (refer to Figure 70). The border ON/OFF is controlled by bit 2 of the block control register (refer to Figure 50). The OUT1 signal is used for border output. The border color for each screen is specified by the border color register. The horizontal size (x) of border is 1TC (OSD clock cycle divided in the pre-divide circuit) regardless of the character font dot size. The vertical size (y) different depending on the screen scan mode and the vertical dot size of character font.
Notes 1 : There is no border for the extra font. 2 : The border dot area is the shaded area as shown in Figure 72. In the EXOSD mode, top and bottom of character font display area is not bordered. 3 : When the border dot overlaps on the next character font, the character font has priority (refer to Figure 73 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 73 B). 4 : The border is not displayed at right side of the most right dot in the display area of the 40th character (the character located at the most right of the block).
All bordered
Fig. 70. Example of border display
Shadow bordered
y x
Scan mode Border dot size Vertical dot size of character font Horizontal size (x) Vertical size (y) Normal scan mode Bi-scan mode
1/2H
1H , 2H , 3H
1/2H , 1H , 2H , 3H
1TC (OSD clock cycle divided in pre-divide circuit)
1/2H
1H
1H
Fig. 71. Horizontal and vertical size of border
65
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD mode
EXOSD mode
16 dots
16 dots
Character font area
20 dots 20 dots
1 dot width of border
1 dot width of border 1 dot width of border 1 dot width of border
Fig. 72. Border area
7
0 Border color register (FC : address 021B16)
Border color R control bit 0 : No output 1 : Output Border color G control bit 0 : No output 1 : Output Border color B control bit 0 : No output 1 : Output Border color I1 control bit 0 : No output 1 : Output Border color I2 control bit 0 : No output 1 : Output
Character boundary B
Character boundary A
Character boundary B
Fig. 73. Border priority
Fig. 74. Structure of border color register
66
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(11) Multiline Display
The M37270MF-XXXSP can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. The mode in which an OSD interrupt occurs is different depending on the setting of the raster color register (refer to Figure 81). * When bit 7 of the raster color register is "0" An OSD interrupt occurs at the end of block display in the OSD and the EXOSD mode. * When bit 7 of the raster color register is "1" An OSD interrupt occurs at the end of block display in the CC mode.
Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register (addresses 00D016 to 00DF16), an OSD interrupt request does not occur (refer to Figure 75 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 75 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 75 (C)).
Block 1 (on display) Block 2 (on display) Block 3 (on display) Block 4 (on display)
"OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request"
Block 1 (on display) Block 2 (on display) Block 3 (off display) Block 4 (off display)
"OSD interrupt request" "OSD interrupt request" No "OSD interrupt request" No "OSD interrupt request"
On display (OSD interrupt request occurs at the end of block display)
Off display (OSD interrupt request does not occur at the end of block display)
Block 1 "OSD interrupt request" Block 1 Block 2
No "OSD interrupt request" "OSD interrupt request"
Block 2 "OSD interrupt request" Block 3 "OSD interrupt request"
Window In CC mode (B) (C)
Fig. 75. Note on occurence of OSD interrupt
67
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(12) Automatic Solid Space Function
This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area : * the character area except character code "00916 " * the character area on the left and right sides of the character area except character code "00916 " This function is turned on and off by bit 4 of the OSD control register (refer to Figure 49).
Notes 1 : Blank is disabled on the left side of the 1st character and on the right side of the 40th character of each block. 2 : When using this function, set "00916" to the 40th character.
Table 18. Setting for automatic solid space Bit 4 of OSD control register Bit 7 of block control register Bit 4 of color code 1 OUT1 output signal 0 Character font part OUT2 output signal OFF 0 1 Character display area OFF Character display area OFF Solid space 0 Character font part 0 1 1 0 Solid space 0 1 0 Character font part 1 1 1
When setting the character code "00516" as the character A, "00616" as the character B.
(Display memory) Character to be displayed
009 005 009 009 009 006 006
16 16 16 16 16 16 16
***
006 009 009 009
16 16 16 16
(Display screen)
***
1st
2nd
(Note 1) character character
No blank output
39th character
40th character
(Note 2) (Note 1)
Fig. 76. Display screen example of automatic solid space
68
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(13) Scan Mode
M37270MF-XXXSP has the bi-scan mode for corresponding to HSYNC of double speed frequency. In the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. The scan mode is selected by bit 1 of the OSD control register (refer to Figure 49).
Table 19. Setting for scan mode Parameter Bit 1 of OSD control register Vertical display start position Vertical dot size Scan mode Normal scan 0 Value of vertical position register ! 1H 1TC ! 1/2H 1TC ! 1H 2TC ! 2H 3TC ! 3H Bi-scan 1 Value of vertical position register ! 2H 1TC ! 1H 1TC ! 2H 2TC ! 4H 3TC ! 6H
(14) Window Function
This function sets the top and bottom boundary of display limit on a screen. The window function is valid only in the CC mode. The top boundary is set by the window H registers 1 and 2. The bottom boundary is set by the window L registers 1 and 2. This function is turned on and off by bit 5 of the OSD control register (refer to Figure 49). The structure of the window H registers 1 and 2 is shown in Figure 78, the structure of the window L registers 1 and 2 is shown in Figure 79.
Notes 1: Set values except "0016" and "0116" to the window H register 1 when the window H register 2 is "0016." 2: Set the register value fit for the following condition : (WH1 + WH2) < (WL1 + WL2)
ABC F GH
DE I J
EXOSD mode
Top boundary of window
CC mode CC mode CC mode Window
KL P
MNO
QRST
U V WX Y
Screen
OSD mode
Bottom boundary of window
Fig. 77. Example of window function
69
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
7
0 Window H register 1 (WH1 : address 021C16) Control bits of window top boundary (Note) Top boundary position (low-order 8bits) TH!(setting value of low-order 2bits of WH2!16 2 + setting value of high-order 4bits of WH1!161 + setting value of low-order 4bits of WH1!16 0 )
7
0 Window H register 2 (WH2 : address 021E16) Control bits of window top boundary (Note) Top boundary position (high-order 2bits) TH!(setting value of low-order 2bits of WH2 !16 2 + setting value of high-order 4bits of WH1!16 1 + setting value of low-order 4bits of WH1!16 0 )
Note : Set values except "0016" and "0116" to the WH1 when the WH2 is "0016."
Fig. 78. Structure of window H registers
7
0 Window L register 1 (WL1 : address 021D16) Control bits of window bottom boundary (Note) Bottom boundary position (low-order 8bits) TH!(setting value of low-order 2bits of WL2!16 2 +setting value of high- order 4bits of WL1!161 + setting value of low-order 4bits of WL1!160 )
7
0 Window L register 2 (WL2 : address 021F16) Control bits of window bottom boundary (Note) Bottom boundary position (high-order 2bits) TH!(setting value of low-order 2bits of WL2!16 2 + setting value of high-order 4bits of WL1! 161 + setting value of low-order 4bits of WL1!160 )
Note : Set values fit for the following condition : (WH1+WH 2) < ( WL1+ WL2) .
Fig. 79. Structure of window L registers
70
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(15) OSD Output Pin Control
The OSD output pins R, G, B, and OUT1 can also function as ports P52, P53, P54 and P55. Set the corresponding bit of the OSD port control register (address 00CB16) to "0" to specify these pins as OSD output pins, or set it to "1" to specify it as a general-purpose port P5 pins. The OUT2, I1, and I2 can also function as port P10, P15, P16. Set the corresponding bit of the port P1 direction register (address 00C316) to "1" (output mode). After that, switch between the OSD output function and the port function by the OSD port control register. Set the corresponding bit to "1" to specify the pin as OSD output pin, or set it to "0" to specify as port P1 pin. The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, I1, I2, OUT1 and OUT2 can be specified with the I/O polarity control register (address 021716) . Set a bit to "0" to specify positive polarity; set it to "1" to specify negative polarity (refer to Figure 61). The structure of the OSD port control register is shown in Figure 80.
7 0 0 OSD port control register (PF : address 00CB16)
Port P15 output signal selection bit 0 : Port P15 output 1 : I1 signal output Port P16 output signal selection bit 0 : Port P16 output 1 : I2 signal output Port P52 output signal selection bit 0 : R signal output 1 : Port P52 output Port P53 output signal selection bit 0 : G signal output 1 : Port P53 output Port P54 output signal selection bit 0 : B signal output 1 : Port P54 output Port P55 output signal selection bit 0 : OUT1 signal output 1 : Port P55 output Port P10 output signal selection bit 0 : Port P10 output 1 : OUT2 signal output Fix this bit to "0."
Fig. 80. Structure of OSD port control register
71
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(16) Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. Since each of the R, G, B, I1, I2, OUT1, and OUT2 pins can be switched to raster coloring output, 7 raster colors can be obtained. If the OUT1 pin has been set to raster coloring output, a raster coloring signal is always output during 1 horizontal scanning period. This setting is necessary for erasing a background TV image. If the R, G, B, I1, and I2 pins have been set to output, a raster coloring signal is output in the part except a no-raster colored character (in Figure 82, a character "1") during 1 horizontal scanning period. This ensures that character colors are not mixed with the raster color. The structure of the raster color register is shown in Figure 81, the example of raster coloring is shown in Figure 82.
7 0 Raster color register (RC : address 021816) Raster color R control bit 0 : No output 1 : Output Raster color G control bit 0 : No output 1 : Output Raster color B control bit 0 : No output 1 : Output Raster color I1 control bit 0 : No output 1 : Output Raster color I2 control bit 0 : No output 1 : Output Raster color OUT1 control bit 0 : No output 1 : Output Raster color OUT2 control bit 0 : No output 1 : Output OSD interrupt source selection bit 0 : Interrupt occurs at end of OSD or EXOSD block display 1 : Interrupt occurs at end of CC mode block display
Fig. 81. Structure of raster color register
: Character color "RED" (R) : Border color "GREEN" (G) : Background color "MAGENTA" (R and B) : Raster color "BLUE" (R and OUT1)
A
A'
HSYNC OUT1 R G B
Fig. 82. Example of raster coloring
Signals across A-A'
72
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
INTERRUPT INTERVAL DETERMINATION FUNCTION
The M37270MF-XXXSP incorporates an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter as shown in Figure 83. Using this counter, it determines an interval or a pulse width on the INT1 or INT2 (refer to Figure 85). The following describes how the interrupt interval is determined. 1. The determination mode is selected by using bit 5 of the interrupt interval determination control register (address 021216). When this bit is set to "0," the interrupt interval determination mode is selected; when the bit is set to "1," the pulse width determination mode is selected. 2. The interrupt input to be determined (INT1 input or INT2 input) is selected by using bit 2 in the interrupt interval determination control register (address 021216). When this bit is cleared to "0," the INT1 input is selected ; when the bit is set to "1," the INT2 input is selected. 3. When the INT1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control register ; when the INT2 input is to be determined, the polarity is selected by using bit 4 of the interrupt interval determination control register.
When the relevant bit is cleared to "0," determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to "1," determination is made of the interval of a negative polarity (falling transition). 4. The reference clock is selected by using bit 1 of the interrupt interval determination control register. When the bit is cleared to "0," a 32s clock is selected ; when the bit is set to "1," a 16s clock is selected (based on an oscillation frequency of 8MHz in either case). 5. Simultaneously when the input pulse of the specified polarity (rising or falling transition) occurs on the INT1 pin (or INT2 pin), the 8-bit binary up counter starts counting up with the selected reference clock (32s or 16s). 6. Simultaneously with the next input pulse, the value of the 8-bit binary up counter is loaded into the interrupt interval determination register (address 021116) and the counter is immediately reset ("0016"). The reference clock is input in succession even after the counter is reset, and the counter restarts counting up from "0016". 7. When count value "FE16" is reached, the 8-bit binary up counter stops counting. Then, simultaneously when the next reference clock is input, the counter sets value "FF16" to the interrupt interval determination register. The reference clock is generated by setting bit 0 of the PWM mode register 1 to "0."
73
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
16s 32s RE1 INT2 (Note) INT1 (Note) RE2 8
Selection gate : Connected to black colored side at rest.
Control circuit
8-bit binary up counter (8) RE0 8
Interrupt interval determination register(8) (Address 021116)
Data bus
RE: Input interval determination control register Note: The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles. Fig. 83. Block diagram of interrupt interval determination circuit
7
0
Interrupt interval determination control register (RE : address 021216) Interrupt interval determination circuit operation control bit 0 : Stopped 1 : Operating Reference clock control selection bit (at f(XIN) = 8MHz) 0 : 32s 1 : 16s External interrupt input pin selection bit 0 : INT1 input 1 : INT2 input INT1 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input INT2 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input Interrupt interval determination mode switch bit 0 : Interrupt interval determination mode 1 : Pulse width determination mode INT3 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input A-D conversion * INT3 interrupt source selection bit 0 : INT3 interrupt 1 : A-D conversion interrupt
INT1 or INT2 input RE5 0 0 1 1 REi 0 1 0 1
Count interval
REi : Bit i (i = 3, 4) of interrupt interval determination control register (address 021116)
Fig. 85. Setting value of interrpt interval determination control register and measuring interval
Fig. 84. Structure of interrupt interval determination control register
74
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
RESET CIRCUIT
The M37270MF-XXXSP is reset according to the sequence shown in Figure 87. It starts the program from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address, when the RESET pin is held at "L" level for 2 ms or more while the power source voltage is 5 V 10 % and the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and then returned to "H" level. The internal state of microcomputer at reset are shown in Figure 88. An example of the reset circuit is shown in Figure 86. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. Poweron 4.5 V Power source voltage 0 V
Reset input voltage 0 V
0.9 V
33 1 5
M51953AL
Vcc
36
RESET
4 3 0.1 F 32
Vss
M37270MF-XXXSP Fig. 86. Example of reset circuit
XIN RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) ? ? ? ?
01, S 01, S-1 01, S-2 FFFE FFFF
ADH, ADL
Reset address from the vector table ? ? ? ADL ADH
Notes 1 : f(XIN) and f( ) are in the relation : f(XIN) = 2*f ( ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected in hardware. At this time, "FF16" is set in timer 3 and "0716" is set to timer 4. Timer 3 counts down with f(X IN)/16, and reset state is released by the timer 4 overflow signal.
Fig. 87. Reset sequence
75
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Address Contents of register Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register OSD port control register OSD control register Horizontal register Caption position register Start bit position register Window register Sync slice register Data register 1 Data register 2 Clock run-in register 1 Clock run-in register 2 (00C116) (00C316) (00C516) (00C716) 0 0 (00C916) 0 0 (00CB16) (00CE16) (00CF16) (00E016) (00E116) (00E216) (00E316) (00E416) (00E516) (00E616) (00E716) 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00 0 I 2C address register I 2 C status register I 2C control register I 2 C clock control register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Clock run-in detect register 3 PWM mode register 1 PWM mode register 2 Timer 5 Timer 6 Sync pulse counter register Data slicer control register 3 Serial I/O mode register Clock source control register I/O polarity control register Raster color register Extra font color register Border color register Processor status register Program counter
Address (00F716)
Contents of register 0016
(00F816) 0 0 0 1 0 0 0 V (00F916) 0016 (00FA16) 0016 (00FB16) 0 0 1 1 1 1 0 0 (00FC16) (00FD16) (00FE16) (00FF16) (020816) (020A16) (020B16) (020C16) (020D16) (020F16) (021016) 000000 0 0016 000 00 0 0 0016 000 00 0 0 0 0016 0716 FF16 000000 0016 0016 0016 0016 0
Clock run-in detect register 1 (00E816)
Interrupt interval determination control register (021216) (021316) (021616)
Clock run-in detect register 2 (00E916) 0 0 0 0 1 0 0 1 Data slicer control register 1 (00EA16) 0016 Data slicer control register 2 (00EB16) V 0 V 0 0 V 0 0 (00EC16) Data register 3 0016 (00ED16) Data register 4 0016 A-D control register Timer 1 Timer 2 Timer 3 Timer 4 Timer mode register 1 Timer mode register 2 (00EF16) 0 (00F016) (00F116) (00F216) (00F316) (00F416) (00F516) 01 FF16 0716 FF16 0716 0016 0016 0
(021716) V 0 0 0 0 0 0 0 (021816) (021916) (021B16) 0016 00000 00000
(PS) V V V V V 1 V V (PCH) (PCL)
Contents of address FFFF16 Contents of address FFFE16
Note : The contents of all other registers and RAM are undefined at reset, so set their initial values.
V
Undefined Unused bit
Fig. 88. Internal state of microcomputer at reset
76
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Ports P03, P10, P15-P17, P2, P30, P31
Direction register
CMOS output
Data bus
Port latch
Ports P03, P10, P15-P17, P2, P30, P31 Note : Each port is also used as below : P10 : OUT2 P15 : I1 P16 : I2/INT3 P17 : SIN P24-P26 : AD3-AD1
Ports P00-P02, P04-P07
N-channel open-drain output
Direction register
Ports P00-P02, P04-P07
Data bus
Port latch
Note : Each port is also used as below : P00-P02 : PWM4-PWM6 P04-P07 : PWM0-PWM3
Ports P11-P14
N-channel open-drain output
Direction register
Port P11-P14
Data bus
Port latch
Note : Each port is also used as below : P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2
Fig. 89. I/O pin block diagram (1)
77
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
SOUT, SCLK
N-channel open-drain output
Direction register
Ports SOUT, SCLK
Data bus
Note : Each pin is also used as below : SOUT : P45 SCLK : P46
HSYNC, VSYNC
Schmidt input
R, G, B, OUT1
CMOS output
Internal circuit
HSYNC, VSYNC
Internal circuit
R, G, B, OUT1 Note : Each pin is also used as below : R : P52 B : P54 G : P53 OUT1 : P55
Ports P40-P44
Data bus
Ports P40-P44 Note : Each port is also used as below : P40 : AD4 P41 : INT2 P42 : TIM2 P43 : TIM3 P44 : INT1
N-channel open-drain output
Ports P32, P47, P50, P51, P56, P57, P65-P67
Data bus
Port latch
Ports P50, P60-P62
Data bus
Port latch
Note : Port P50 is also used as PWM7
Fig. 90. I/O pin block diagram (2)
78
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
CLOCK GENERATING CIRCUIT
The M37270MF-XXXSP has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. When using XCIN-XCOUT as subclock, clear bits 5 and 4 of the clock source control register to "0." To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to "1."
(3) Low-Speed Mode
If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to "1." When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN-XCOUT drivability can be reduced, allowing even lower power consumption (60 A with f (XCIN) = 32kHz). To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to "0." At reset, this bit is set to "1" and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to "1" by software before executing.
Oscillation Control (1) Stop mode
The built-in clock generating circuit is shown in Figure 56. When the STP instruction is executed, the internal clock stops at "H" level. At the same time, timers 3 and 4 are connected in hardware and "FF16" is set in the timer 3, "0716" is set in the timer 4. Select f(XIN)/16 or f(XCIN)/16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to "0" before the execution of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to disabled ("0") before execution of the STP instruction. The oscillator restarts when external interrupt is accepted, however, the internal clock keeps its "H" level until timer 4 overflows. Because this allows time for oscillation stabilizing when a ceramic resonator or a quartz-crystal oscillator is used.
M37270MF-XXXSP XCIN
Rf
XCOUT
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig. 91. Ceramic resonator circuit example
(2) Wait mode
M37270MF-XXXSP XCIN XCOUT XIN Open External oscillation circuit or external pulse Vcc Vss XOUT Open External oscillation circuit Vcc Vss
When the WIT instruction is executed, the internal clock stops in the "H" level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. (1) VSYNC interrupt (2) OSD interrupt (3) Timers 1 and 2 interrupts using P42/TIM2 pin input as count source (4) Timer 3 interrupt using P43/TIM3 pin input as count source (5) Data slicer interrupt (6) Multi-master I2C-BUS interface interrupt (7) f(XIN)/4096 interrupt (8) All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source (9) All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source (10) A-D conversion interrupt
Fig. 92. External clock input circuit example
79
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
XCIN
XCOUT
XIN
OSC1 oscillating mode selection bits (Notes 1, 4) XOUT "1" 1/2 "0" Internal system clock selection bit (Notes 1, 3) 1/8 "1" "0"
Timer 3 count stop bit (Notes 1, 2) Timer 3
Timer 4 count stop bit (Notes 1, 2) Timer 4
Timer 3 count source selection bit (Notes 1, 2) Timing (Internal clock)
Main clock (XIN-XOUT) stop bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Q S S Q Q S
Reset STP instruction
R
STP instruction
WIT instruction
R
R
Reset Interrupt disable flag I Interrupt request
Notes 1 : The value at reset is "0." 2 : Refer to the structure of timer mode register 2. 3 : Refer to the structure of CPU mode register (next page). 4 : Refer to the structure of clock source control register.
Fig. 93. Clock generating circuit block diagram
80
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Reset
High-speed operation start mode
WIT instruction 8MHz oscillating 32kHz oscillating is stopped ("H") Timer operating Interrupt External INT, timer interrupt, or SI/O interrupt 8MHz oscillating 32kHz oscillating f( ) = 4MHz
STP instruction 8MHz stopped 32kHz stopped is stopped ("H") Interrupt (Note 1) External INT CM7 = 0
CM7 = 1
WIT instruction 8MHz oscillating 32kHz oscillating is stopped ("H") Timer operating (Note 3) 8MHz oscillating 32kHz oscillating f( ) = 16kHz Interrupt
STP instruction 8MHz stopped 32kHz stopped is stopped ("H") Interrupt (Note 2) CM6 = 0 The program must allow time for 8MHz oscillation to stabilize
CM6 = 1
8MHz stopped 32kHz oscillating is stopped ("H") Timer operating (Note 3)
WIT instruction 8MHz stopped 32kHz oscillating f( ) = 16kHz Interrupt
STP instruction 8MHz stopped 32kHz stopped = stopped ("H") Interrupt (Note 2)
CPU mode register (Address : 00FB16) CM6 : Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped CM7 : Internal system clock selection bit 0 : XIN-XOUT selected (high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The indicates the internal clock. Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock divided by 8 is used as the timer count source, the frequency of the count source is 2kHz.
Fig. 94. State transitions of system clock
81
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
DISPLAY OSCILLATION CIRCUIT
The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 4 of the clock source control register (address 021616).
ADDRESSING MODE
The memory access is reinforced with 17 kinds of addressing modes. Refer to the SERIES 740 User's Manual for details.
MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to the SERIES 740 User's Manual for details.
PROGRAMMING NOTES
(1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor ( 0.1 F) directly between the VCC pin-VSS pin, AVCC pin-VSS pin, and the VCC pin-CNVSS pin using a thick wire.
OSC1
OSC2
L C1 C2
Fig. 95. Display oscillation circuit
AUTO-CLEAR CIRCUIT
When power source is supplied, the auto-clear function can be performed by connecting the following circuit to the RESET pin.
Circuit example 1
Vcc
RESET
Vss
Circuit example 2
RESET
Vcc
Vss
Note : Make the level change from "L" to "H" at the point at which the power source voltage exceeds the specified voltage. Fig. 96. Auto-clear circuit example
82
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies)
PROM Programming Method
The built-in PROM of the One Time PROM version (blank) and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Product M37270FSP Name of Programming Adapter PCA7401
The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 97 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution : The screening temperature is far higher than the storage temperature. Never expose to 150C exceeding 100 hours.
Fig. 97. Programming and testing of One Time PROM version
83
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC, AVCC VI VI Input voltage Input voltage Parameter Power source voltage VCC, AVCC CNVSS P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P64, OSC1, XIN, HSYNC, VSYNC, RESET, CVIN P03, P10-P17, P20-P27, P30, P31, P32, P47, P51, P56, P57, P60-P62, P65-P67, R, G, B, OUT1, SOUT, SCLK, XOUT, OSC2 P00-P02, P04-P07, P50, P60-P62 R, G, B, OUT1, OUT2, P03, P15-P17, P20-P27, P30, P31 R, G, B, OUT1, OUT2, P03, P15-P17, P20-P27, P56, P57, P66, P67, SOUT, SCLK P11-P14 P00-P02, P04-P07, P32, P47, P50, P51, P60-P62 P30, P31 Ta = 25 C Conditions All voltages are based on VSS. Output transistors are cut off. Ratings -0.3 to 6 -0.3 to 6 -0.3 to VCC + 0.3 Unit V V V
VO
Output voltage
-0.3 to VCC + 0.3
V
VO IOH IOL1
Output voltage Circuit current Circuit current
-0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2)
V mA mA
IOL2 IOL3 IOL4 Pd Topr Tstg
Circuit current Circuit current Circuit current Power dissipation
0 to 6 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 -10 to 70 -40 to 125
mA mA mA mW C C
Operating temperature Storage temperature
RECOMMENDED OPERATING CONDITIONS (Ta = -10 C to 70 C, VCC = 5 V 10 %, unless otherwise noted)
Symbol VCC, AVCC VCC, AVCC VSS VIH1 Parameter Power source voltage (Note 4), During CPU, OSD, data slicer operation RAM hold voltage (when clock is stopped) Power source voltage "H" input voltage P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P64, HSYNC, VSYNC, RESET, XIN, OSC1 "H" input voltage P11-P14 (When using I2C-BUS) "L" input voltage P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P63, P64 "L" input voltage SCL1, SCL2, SDA1, SDA2, (When using I2C-BUS) "L" input voltage (Note 6) P41-P44, P46, P17, HSYNC, VSYNC, RESET, XIN, OSC1 "H" average output current (Note 1) R, G, B, OUT1, OUT2, P03, P15-P17, P20-P27, P30, P31 "L" average output current (Note 2) R, G, B, OUT1, OUT2, P03, P15-P17, P20-P27, P47, P51, P56, P57, P65-P67, SOUT, SCLK "L" average output current (Note 2) P11-P14 "L" average output current (Note 2) P00-P02, P04-P07, P50, P60-P62 "L" average output current (Note 3) P30, P31 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for sub-clock operation) XCIN Oscillation frequency (for OSD) OSC1 LC oscillating mode Ceramic oscillating mode Input frequency TIM2, TIM3, INT1, INT2, INT3 Input frequency SCLK Input frequency SCL1, SCL2 Input frequency Horizontal sync. signal of video signal Input amplitude video signal CVIN Min. 4.5 2.0 0 0.8VCC Limits Typ. 5.0 0 Max. 5.5 5.5 0 VCC Unit V V V V
VIH2 VIL1 VIL2 VIL3 IOH IOL1
0.7VCC 0 0 0
VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2
V V V V mA mA
IOL2 IOL3 IOL4 fCPU fCLK fOSD fhs1 fhs2 fhs3 fhs4 VI
7.9 29 11.0 26.5
8.0 32 27.0
15.262 1.5
15.734 2.0
6 1 10 8.1 35 27.0 27.5 100 1 400 16.206 2.5
mA mA mA MHz kHz MHz kHz MHz kHz kHz V
84
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ELECTRIC CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted)
Symbol ICC Parameter Power source current System operation Test conditions VCC = 5.5 V, CRT OFF f(XIN) = 8 MHz Data slicer OFF CRT ON Data slicer ON VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Wait mode VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Stop mode VOH VOL "H" output voltage "L" output voltage R, G, B, OUT1, OUT2, P03, P15-P17, P20-P27, P30, P31 R, G, B, OUT1, OUT2, SOUT, SCLK, P00-P07, P15-P17, P20-P27, P50, P32, P47, P56, P57, P60-P62, P65-P67 P30, P31 P11-P14 RESET VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = -0.5 mA VCC = 4.5 V IOL = 0.5 mA 2.4 0.4 Limits Min. Typ. 15 30 60 Max. 30 mA 45 200 A Unit
2 25
4 100
mA
A 1 10 V
"L" output voltage "L" output voltage VT+-VT- Hysteresis
VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V VCC = 5.0 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VI = 12 V VCC = 4.5 V IOL = 3 mA IOL = 6 mA 0.5 0.5
3.0 0.4 0.6 0.7 1.3 5
V
Hysteresis (Note 6) HSYNC, VSYNC, P41-P44, P46, P11-P14, P17 IIZH "H" input leak current RESET, P03, P10-P17, P20-P27, P30, P31, P40-P46, P63, P64, HSYNC, VSYNC "L" input leak current RESET, P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P63, P64, HSYNC, VSYNC "H" input leak current P00-P02, P04-P07, P50, P60-P62
V
A
IIZL
5
A A
IIZH RBS
10 130
I2 C-BUS*BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2)
Notes 1: The total current that flows out of the IC must be 20 or less. 2: The total input current to IC (IOL1 + IOL2 + IOL3) must be 20 mA or less. 3: The total average input current for ports P30, P31 to IC must be 10 mA or less. 4: Connect 0.1 F or more capacitor externally across the power source pins VCC-VSS and AVCC-VSS so as to reduce power source noise. Also connect 0.1 F or more capacitor externally across the pins VCC-CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P16, P41-P44 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11-P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P17 and P46 have the hysteresis when these pins are used as serial I/O pins.
85
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
A-D CONVERTER CHARACTERISTICS
Symbol -- -- -- VOT VFST TCONV VREF RLADDER VIA Resolution Non-linearity error Differential non-linearity error Zero transition error Full-scale transition error Conversion time Reference voltage Ladder resistor Analog input current Parameter
(VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted) Test conditions Limits Min. 0 0 VCC = 5.12V IOL (SUM) = 0mA VCC = 5.12V 0 0 12.25 Typ. Max. 8 2 0.9 2 4 12.5 VCC 25 0 VREF Unit bits LSB LSB LSB LSB s V k V
MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Symbol tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Bus free time Hold time for START condition "L" period of SCL clock Rising time of both SCL and SDA signals Data hold time "H" period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition 250 4.7 4.0 0 4.0 300 Parameter Standard clock mode High-speed clock mode Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit s s s ns s s ns ns s s
Note: Cb = total capacitance of 1 bus line
SDA tHD:STA tSU:STO
tBUF tLOW p SCL S
tR
tF Sr p
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
Fig. 98. Definition diagram of timing on multi-master I2C-BUS
86
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PACKAGE OUTLINE
87
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
GZZ-SH09-39B < 51A0 > Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37270MF-XXXSP MITSUBISHI ELECTRIC
Date :
Receipt
Section head signature Supervisor signature
Note : Please fill in all items marked g .
signature Issuance
Company name
TEL ( Date : )
Submitted by
Supervisor
g Customer
Date issued
g1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM EPROM type (indicate the type used)
(hexadecimal notation)
27C101
EPROM address 0000016 Product name 0000F16 0100016 0FFFF16 1080016
ASCII code : `M37270MF -'
data ROM 60K bytes
OSD ROM
1E43F16
(1) (2)
Set "FF16" in the shaded area. Write the ASCII codes that indicates the product name of "M37270MF-" to addresses 0000
16
to 000F16.
EPROM data check item (Refer the EPROM data and check " " in the appropriate box) q Do you set "FF16" in the shaded area ? Yes q Do you write the ASCII codes that indicates the product Yes name of "M37270MF-" to addresses 0000 16 to 000F16 ?
g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (64P4B for M37270MF-XXXSP) and attach to the mask ROM confirmation form.
(1/4)
88
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
GZZ-SH09-39B < 51A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37270MF-XXXSP MITSUBISHI ELECTRIC
Writing the product name and character ROM data onto EPROMs
Addresses 00000 16 to 0000F16 store the product name, and addresses 10800 16 to 1E43F16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly.
1. Inputting the name of the product with the ASCII code ASCII codes `M37270MF-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = `3' = `7' = `2' = `7' = `0' = `M' = `F' =
4D 33 37 32 37 30 4D 46
16 16 16 16 16 16 16 16
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
`-' = 2 D FF FF FF FF FF FF FF
16 16 16 16 16 16 16 16
2. Inputting the character ROM Input the character ROM data to character ROM. For the character ROM data, see the next page and on.
(2/4)
89
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
GZZ-SH09-39B < 51A0>
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37270MF-XXXSP MITSUBISHI ELECTRIC
Font data must be stored in the proper OSD ROM address according to the following table. (1)OSD ROM address of character font data
OSD ROM address bit Line number / Character code / Font bit
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
0
Line number
Character code
Font bit
Line number = 02 16 to 1516 Character code = 00 16 to 13F16 Font bit = 0 : Left font 1 : Right font Example) The font data "60" (shaded area ) of the character code "AA 16" is stored in address
2
10010100101010100
=1295416.
(2)OSD ROM address of extra font data
OSD ROM address bit Line number / Extra code / Font bit
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
1
Line number
0
0
0
0
Extra code
Font bit
Line number = 00 16 to 1916 Extra code = 00 16 to 1F16 Font bit = 0 : Left font 1 : Right font Example) The font data "03" (shaded area ) of the extra code "0A 16" is stored in address
2
11001010000010101
=1941516.
Left font Right font
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Left font Line number 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516
Right font
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(1) Character code "AA 16"
Line number 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0016 0016 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916
(2) Extra code "0A 16"
(3/4)
90
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
GZZ-SH09-39B < 51A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37270MF-XXXSP MITSUBISHI ELECTRIC
The following OSD ROM addresses must be set "FF." There are no font data in these addresses. 10A8016 to 10BFF16 10E8016 to 10FFF16 1128016 to 113FF16 1168016 to 117FF16 11A8016 to 11BFF16 11E8016 to 11FFF16 1228016 to 123FF16 1268016 to 127FF16 12A8016 to 12BFF16 12E8016 to 12FFF16 1328016 to 133FF16 1368016 to 137FF16 13A8016 to 13BFF16 13E8016 to 13FFF16 1428016 to 143FF16 1468016 to 147FF16 14A8016 to 14BFF16 14E8016 to 14FFF16 1528016 to 153FF16 1568016 to 17FFF16 1804016 to 183FF16 1844016 to 187FF16 1884016 to 18BFF16 18C4016 to 18FFF16 1904016 to 193FF16 1944016 to 197FF16 1984016 to 19BFF16 19C4016 to 19FFF16 1A04016 to 1A3FF16 1A44016 to 1A7FF16 1A84016 to 1ABFF16 1AC4016 to 1AFFF16 1B04016 to 1B3FF16 1B44016 to 1B7FF16 1B84016 to 1BBFF16 1BC4016 to 1BFFF16 1C04016 to 1C3FF16 1C44016 to 1C7FF16 1C84016 to 1CBFF16 1CC4016 to 1CFFF16 1D04016 to 1D3FF16 1D44016 to 1D7FF16 1D84016 to 1DBFF16 1DC4016 to 1DFFF16 1E04016 to 1E3FF16
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91
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
92
MITSUBISHI DATA BOOK SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.3
Sep. First Edition 1996 H-DF319-B Editioned by Committee of editing of Mitsubishi Semiconductor Data Book Published by Mitsubishi Electric Corp., Semiconductor Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. (c)1996 MITSUBISHI ELECTRIC CORPORATION Printed in Japan
REVISION DESCRIPTION LIST
M37270MF-XXXSP M37270EF-XXXSP, M37270EFSP DATA SHEET
Rev. No. 1.0 2.0 First Edition
Revision Description
Rev. date 9708 971130
Information about copyright note, revision number, release date added (last page).
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